1. Technical Field
Embodiments of the present invention relate to programming of test systems with probe cards. More particularly, embodiments of the present invention relate to probe cards with on board features used to test integrated circuits (ICs) on a wafer.
2. Related Art
A wafer testing device typically includes a probe card with probes for electrically contacting pads of ICs on the wafer. The location of the IC contact pads on a wafer, as well as the signals that need to be sent for testing are different for each IC design. In the test system, the length of test lines and components on the probe card should also be considered to best interpret test results. Cost considerations for the test equipment are also important, so designers typically attempt to make only test signal software changes and changes to the probe cards to accommodate different wafer layouts, since replacement of the main test system controller components and operating software are significantly more expensive. Conventional steps to design and program a test system to accommodate different IC configurations on a wafer are considered to follow.
I. IC Design and Wafer Layout Process
Consideration of the wafer layout process, including what IC components are included and how ICs are placed on the wafer defines boundaries for a test system. The test system probe locations for contacting pads on the ICs and signals provided on lines delivering signals to the probes are determined based on the IC wafer layout. One process for layout of ICs on a wafer is described in U.S. Pat. No. 6,539,531, entitled “Method of Designing, Fabricating, Testing and Interconnecting an IC to External Circuit Nodes” to Miller, et al., issued Mar. 25, 2003.
FIG. 1 illustrates a typical prior art process of designing and fabricating an IC on a wafer. A design engineer initially develops a design specification (70) abstractly describing the overall architecture of the IC and then develops a high-level hardware description language (HDL) model of the IC (72). The design engineer also programs a circuit simulator (74) to simulate circuit behavior based on the HDL circuit model.
Thereafter, the design engineer usually employs computer-aided logic synthesis tools (76) to convert the high-level HDL circuit model into a technology-specific, behavioral model of the circuit such as a netlist. A netlist model typically describes the behavior of circuit components based on models provided by a cell library (80). Each cell of cell library (80) includes both netlist-level behavioral models and structural models (mask layouts) for each circuit component that may be incorporated into an IC. Cell library (80) may include cells describing low level circuit components such as individual resistors and transistors as well as higher level standard circuit components such as logic gates, memories and central processing units.
During the iterative, synthesis process the design engineer uses a simulator and other tools to verify circuit operation based on the netlist model (82) and may iteratively adjust the HDL model to produce a netlist model that satisfies various constraints.
Having verified the logic and timing of the netlist circuit model, the design engineer employs additional computer-aided design tools to establish a floorplan (78) fixing locations of the IC's input/output (I/O). Placement and routing tools establish the detailed layout of the various layers of IC, outlining how the conductors interconnecting those cells are to be routed (86). In addition to a behavioral model of a circuit component, each component cell of cell library (84) also includes a structural model (mask layout) of the circuit component that can be incorporated into the IC layout. The computer aided design (CAD) tools vary the IC design, subjecting each variation to simulation and verification (88) to determine how well it satisfies the specification. The floorplan output is a structural model of the IC in the form of a set of masks telling an IC manufacturer how to fabricate the various layers of the IC.
II. Test System Design and Fabrication
Once the IC design for a wafer is complete, the layout of pads and the pin functions of the pads are used to construct and program a test system to test components on the wafer during fabrication. To minimize costs, a replaceable probe card is typically constructed as an interface between a test system controller and the wafer since cost for structural modifications to a test system controller are significantly higher.
The probe card includes probes and internal channel routing lines to link the probes to connectors linking to the test system controller. Components such as switches and capacitors may be included in the channel paths. Placement and routing of channels is performed prior to creation of masks for fabricating layers of the probe card. Once the design is complete, probe cards can be created and fabricated using a number of methods to create micro-electro-mechanical systems (MEMs) with probe elements, the probes including, for example, lithographic spring contacts, wire bonds, needle probes and cobra probes. The test system controller can then be programmed to generate appropriate test signals to provide through the channels of the probe card, and to analyze signals received to interpret test results.
For reference, FIG. 2 shows a block diagram of a typical test system using a probe card for testing devices under test (DUTs) on a semiconductor wafer. The test system includes a test system controller 4, which may be an Automatic Test Equipment (ATE) tester or general purpose computer, connected by a communication cable 6 to a test head 8. The test system further includes a prober 10 made up of a stage 12 for mounting a wafer 14 being tested, the stage 12 being movable to contact the wafer 14 with probes 16 on a probe card 18. The prober 10 includes the probe card 18 supporting probes 16 which contact DUTs formed on the wafer 14.
In the test system, test signals are generated by the test system controller 4 and transmitted through the communication cable 6, test head 8, probe card 18, probes 16 and ultimately to DUTs on the wafer 14. Test data provided from the test system controller 4 is divided into the individual test channels provided through the cable 6 and separated in the test head 8 so that each channel is carried to a separate one of the probes 16. The channels from the test head 8 are linked by flexible cable connectors 24 to the probe card 18. The probe card 18 then links each channel to a separate one of the probes 16. Test results are then provided from DUTs on the wafer back through the probe card 18 to the test head 8 for transmission back to the test system controller 4. Once testing is complete, the wafer is diced up to separate the DUTs.
FIG. 3 shows a cross sectional view of components of a typical probe card 18. The probe card 18 is configured to provide both electrical pathways and mechanical support for the spring probes 16 that will directly contact the wafer. The probe card electrical pathways are provided through a printed circuit board (PCB) 30, an interposer 32, and a space transformer 34. Test data from the test head 8 is provided through flexible cable connectors 24 typically connected around the periphery of the PCB 30. Channel transmission lines 40 distribute signals from the connectors 24 horizontally in the PCB 30 to contact pads on the PCB 30 to match the routing pitch of pads on the space transformer 34. The interposer 32 includes a substrate 42 with spring probe electrical contacts 44 disposed on both sides. The interposer 32 electrically connects individual pads on the PCB 30 to pads forming a land grid array (LGA) on the space transformer 34. Traces 46 in a substrate 45 of the space transformer 34 distribute or “space transform” connections from the LGA to spring probes 16 configured in an array.
Mechanical support for the electrical components is provided by a back plate 50, bracket (Probe Head Bracket) 52, frame (Probe Head Stiffener Frame) 54, leaf springs 56, and leveling pins 62. The back plate 50 is provided on one side of the PCB 30, while the bracket 52 is provided on the other side and attached by screws 59. The leaf springs 56 are attached by screws 58 to the bracket 52. The leaf springs 56 extend to movably hold the frame 54 within the interior walls of the bracket 52. The frame 54 then includes horizontal extensions 60 for supporting the space transformer 34 within its interior walls. The frame 54 surrounds the probe head and maintains a close tolerance to the bracket 52 such that lateral motion is limited.
Leveling pins 62 complete the mechanical support for the electrical elements and provide for leveling of the space transformer 34. The leveling pins 62 are adjusted so that brass spheres 66 provide a point contact with the space transformer 34. The spheres 66 contact outside the periphery of the LGA of the space transformer 34 to maintain isolation from electrical components. Leveling of the substrate is accomplished by precise adjustment of these spheres through the use of advancing screws, or leveling pins 62. The leveling pins 62 are screwed through supports 65 in the back plate 50 and PCB 30. Motion of the leveling pin screws 62 is opposed by leaf springs 56 so that spheres 66 are kept in contact with the space transformer 34. FIG. 4 shows an exploded assembly view of components of the probe card of FIG. 3. FIG. 5 shows a perspective view of the opposing side of PCB 30 from FIG. 4, illustrating the arrangement of connectors 24 around its periphery.
Alternative embodiments of probe card assemblies are described in U.S. Pat. No. 6,624,648, entitled “Probe Card Assembly” to Eldridge, et al., issued Sep. 23, 2003, U.S. Pat. No. 6,615,485, entitled “Probe Card Assembly and Kit and Methods of Making Same” to Eldridge, et al., issued Sep. 9, 2003, U.S. Pat. No. 6,838,893, entitled “Probe Card Assembly” to Khandros, Jr., et al., issued Jan. 4, 2005, and U.S. Pat. No. 6,856,150, entitled “Probe Card With Coplanar Daughter Card” to Sporck, et al., issued Feb. 15, 2005.
III. Wafer Testing
Test systems are typically used in one instance to test memory components, such as dynamic random access memory (DRAM) on a wafer during manufacture while ICs are still in the form of a die on the wafer before the wafer is diced up into individual chips. “Repairable” DRAMs typically have one or more “spare” rows or columns of memory cells that can replace a row or column with defective cells. Wafer testing can include a “redundancy analysis” to determine how to best allocate spare rows or columns to replace the rows or columns containing defective cells. The memory is then repaired using lasers or other means to appropriately alter signal path routing within the IC so that spare rows and/or columns of cells are substituted for rows and columns having defective cells.
When the IC has no repairable memory, the wafer is “diced” to separate the individual die and packaged. The packaged IC may be subjected to a “burn-in” process wherein it is heated in an oven to place it under the kind of heat and voltage stress that it may encounter in its working environment.
A limitation of a typical test system controller with increased density of DUTs on a wafer is that not all DUTs can be tested during a single touch down of a probe card. With advancing technology, more DUTs are fabricated on a single wafer. To avoid the cost of a new test system controller, multiple touchdowns of a test system to the wafer are performed. Multiple touch downs, however, may be undesirable since touchdowns increase the likelihood of damaging the wafer, and touch downs further increase wear on the probes in the test system, which may be expensive to replace.